1. Field of Invention
The present invention generally relates to a delay line degradation protection architecture, especially with built-in ring oscillation apparatus, and more particularly to an in-system delay line ring oscillation apparatus.
2. Description of Prior Art
When a clock path including a delay lock loop circuits that were in use go into an asymmetric stress condition for the time the clock is not toggled, especially conditions including slow exit power down, self-refresh, or any operations requiring delay lock loop circuit reset aftermath. It is hoped on not going into this type of non-clocking state for long periods of time in the past, or hope even/odd number of random event durations are balanced.
In a dynamic random access memory (DRAM) application, for the issue mentioned above, both duty cycle degradation and a tDQSCK (data signal skew to clock signal) timing shift due to degradation stress mismatch are exposed. The same issue can be seen in the clock distribution tree. The issues impact on DRAM lifetime severely considering servers field application randomness.